一直觉得xilinx的ISE开发套件可难看了，一点也不高大上。既然决定学习FPGA，使用xilinx的芯片，那么必须好好了解其开发环境及开发流程。ISE自身带的帮助是最好的教程，没有之一。ISE的帮助，绝对高大上！

1.ISE帮助（Xilinx ISE Help）

    ISE帮助里面是这样分类的。

    Software Overview里面说明了ISE包含的软件及其功能，还有一些介绍，其实没有什么好看的。

    Documentation Overview对xilinx官方的各种关于ISE软件的文档分类，并做了简要介绍，找文档可以到这里找。

    Understanding the ISE Design Flow是ISE设计流程，值得一看，但是实际上很多文档里面都有，反正迟早都会看到。

    Working with ISE Projects和Using the ISE Viewing Environment介绍的软件的操作，不看的话基本也会。什么功能不会可以到这里翻翻。

    后面除了CPLD Design实际上是Design Flow中的具体步骤的实现方法指南，都很有价值。

2.ISE in-Depth Tutorial

    这份文档可以改跟名字，叫做“手把手教你如何使用ISE”，图文并茂，细致入微。这里并不是按照ISE Design Flow走的，而是介绍如何通过两种方式（我发现我不会用schematic……）设计，之后完全按照Design里的步骤来进行的。

   HDL编写

    Edit-Language Templates有很多代码的参考，并且可以直接插入到自己编写的代码中去。

    时序约束

    写约束对FPGA更好的按照要求布局布线是有益处的。

    translating

    During translation, the NGDBuild program performs the following functions:
    ? Converts input design netlists and writes results to a single merged NGD netlist. The merged netlist describes the logic in the design as well as any location and timing constraints.
    ? Performs timing specification and logical design rule checks.
    ? Adds constraints from the User Constraints File (UCF) to the merged netlist.

    I/O location

    采用PlanAhead对I/O进行定义。

    Mapping

    The design is mapped into CLBs and IOBs. Map performs the following functions:
    ? Allocates CLB and IOB resources for all basic logic elements in the design.
    ? Processes all location and timing constraints, performs target device optimizations,
and runs a design rule check on the resulting mapped netlist.

    Timing Analysis

Estimating Timing Goals with the 50/50 Rule
    For a preliminary indication of how realistic your timing goals are, evaluate the design after the map stage. A rough guideline (known as the “50/50 rule”) specifies that the block delays in any single path make up approximately 50% of the total path delay after the design is routed. For example, a path with 10 ns of block delay should meet a 20 ns timing constraint after it is placed and routed.

   Map展开后可以点击 Analyze Post-Map Static Timing对其进行分析。

    Placing and Routing

    After the mapped design is evaluated, the design can be placed and routed. One of two place-and-route algorithms is performed during the Place and Route (PAR) process:
    ? Timing-Driven PAR
    PAR is run with the timing constraints specified in the input netlist, the constraints file, or both.
    ? Non-Timing-Driven PAR
    PAR is run, ignoring all timing constraints.

    Post—Layout Timing

3.ISE Design Flow

    ISE设计流程如下图所示

4.ISE相关文档（部分）

5.总结

    多看看文档。