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Timing_Analyzer学习记录
Timing Analyzer 综述
使用该软件可以在设计中完成以下一些任务:在设计中进行静态时序分析;在映射、布局、布线后都可以立即进行时序分析;可通过GUI/tcl命令行/xtclsh应用/批处理/微控制命令等实现分析;报告指定路径延迟、关键路径延时、电路运行周期、可靠速度/电压/温度等的分布信息;做建立时间和保持时间的分析;有层次化索引用于报告内容的快速定位;可在Technology Viewer 和Floorplan-Implemented中查看指定路径
相关文件特征和流程
输入文件:
- NCD文件:一个FPGA设计的数据文件,映射到芯片后的设计,可能也包含布局和布线信息
- PCF文件:一个约束文件,包含时序约束信息,由MAP自动将UCF信息转换得到
输出文件:
- TWX文件:只能在时序分析器中查看的XML时序分析结果的报告
- TWR文件:文本格式的时序分析结果的报告
- TSI文件:Timing Specification Interaction (TSI) is an ASCII report detailing the interaction between overlapping timing specifications (constraints).
- HTML文件:HTML格式的时序分析结果的报告
- NGD文件:用于探针定位查看的可选项
- UCF文件:用于约束的可选项
常见设计问题:
- 反馈循环;时序约束;时钟偏移;时序冲突;Off-chip delay
基础分析路径类型:时钟频率;输入建立时间;输出时钟传送延时;端口到端口组合延时
- Against Timing Constraints Analysis
- Against Auto Generated Design Constraints Analysis
- Against User Specified Paths by Defining Endpoints
- Against User Specified Paths by Defining Clock and IO Timing
命令行打开时序分析:timingan –ise project.ise –ucf constraints.ucf –ngd design.ngd design.ncd constraints.pcf report.twx.无参数时会弹出对话框进行文件选择
Shortcut | Menu | Command |
F1 | Help | Help Topics |
F10 | Change focus to the menu bar | |
Ctrl+P | File | |
Ctrl+C | Edit | Copy |
F3 | Edit | Find Next |
Ctrl+F4 | Window | Close |
分析流程:
- 映射后静态时序分析:在Processes for Current Source窗口选Generate Post-Map Static Timing
- 布线后静态时序分析:在Processes for Current Source窗口选Generate Post-Place & Route Static Timing
基础操作
- 隐藏工具栏:View > Toolbars >Timing Analyzer
- 查看时钟:Analyze > Clocks
- 查看时序分析设置:Analyze > Settings
- 探针定位显示路径:在TWX文件中点击路径超链接,跳转到电路图相应位置
- Technology View-Exploration Mode:查看路径相关联的器件,选定路径右键后选Show <Implemented | Translated> path to Technology ViewExploration Mode跳转
- Floorplan-Implemented关联显示:打开Floorplan视图,选定网线、元件、路径即实时显示
- 从设计总报告跳转:在报告中选择一个时序约束,即可打开并定位到相关的时序报告信息
- Constraint Improvement Wizard:通过报告中未覆盖约束路径超链接打开,其中给出了提高约束覆盖率的方法和建议
- Timing Improvement Wizard:通过不满足时序约束路径的超链接打开,其中给出了改善延时性能的建议和方法
- 提取时序信息:Analyze > Query Nets or Analyze > Query Timegroups
- 参数设置:颜色、字体(类型/大小/预览)、报告包含内容(Design statistics/Site locations column/Physical names in detailed path/Show Timing Report Tips dialog box)、报告格式(HTML/Text) 、查找方案(Edit > Preferences > Find What Category tab,然后选择Allow Wildcards (*, ?)、Allow Regular Expressions、Match Case)
报告生成和修改
- 创建时序约束分析报告:Analyze > Against Timing Constraints
- 创建指定路径终点分析报告:Analyze > Analyze Against User Specified Paths > by Defining Endpoints
- 创建指定路径时钟和IO时序分析报告:Analyze > Against User Specified Paths > by Defining Clock and IO Timing
- 创建时钟报告:Analyze > Clocks然后File > Save As
- 创建设置报告:Analyze > Settings然后File > Save As
- UCF和PCF约束全忽略分析报告:Analyze > Against Auto Generated Constraints
- 创建未布线延时:Analyze > Query Nets
- 时间组报告:Analyze > Query Timegroups
- 报告参数设置:Edit > Preferences选择Timing Analyzer
- 创建约束对应路径报告:Analyze > Against Timing Constraints选择Generate constraints interaction report
- 查看约束对应路径报告:可用于理解多约束的优先级别(从低到高)
- Unconstrained path analysis
- PERIOD or FREQUENCY, allclocknets
- PERIOD or FREQUENCY, time group
- PERIOD or FREQUENCY, net
- OFFSET IN/OUT, global
- OFFSET IN/OUT, time group
- OFFSET IN/OUT, pad
- MAXDELAY path, with pre-defined FROM and TO groups
- MAXDELAY path, with user-defined FROM or TO group
- MAXDELAY path, with user-defined FROM and TO groups
- MAXDELAY path, with intermediate (THRU) points
- TIG path
- 创建未约束路径报告:Analyze > Against Timing Constraints选择Report Unconstrained Path option
- 创建Offsets Summary Report
- 查看时序分析报告:设计信息头、所有报告信息、所有警告信息、所有约束信息和每个约束覆盖的路径、未满足约束条件约束量、数据报告、约束覆盖时序分析总结、时序分析设置
- 可行操作:启/禁时序约束、用户指定路径分析、使用路径追踪、通过网线进行路径过滤、重置所有路径过滤(Analyze > Reset All Path Filters)
- 路径名称和简写
Abbreviation | Path Type | Default |
reg_sr_r | Asynchronous Set/Reset Recovery times | Disabled |
reg_sr_o | Asynchronous Set/Reset Propagation times to output | Disabled |
lat_d_q | Data to output for transparent latch | Disabled |
ram_d_o | RAM data to output | Disabled |
ram_we_o | RAM WE to output | Enabled |
tbuf_t_o | TBUF 3-state control to output | Enabled |
tbuf_i_o | TBUF input to output | Enabled |
io_pad_i | I/O pad to input | Enabled |
io_t_pad | I/O 3-state control to pad | Enabled |
io_o_i | Bidirectional 3-state I/O output to input | Enabled |
io_o_pad | I/O output to pad | Enabled |
reg_sr_clk | Synchronous Set/Reset setup/hold | Enabled |
Tcl命令
delete | Deletes analysis. |
disable_constraints | Disables a physical timing constraint from timing analysis. |
disable_cpt | Disables specified or all components associated with path tracing control from timing analysis. |
enable_constraints | Enables a physical timing constraint from timing analysis. |
enable_cpt | Enables specified or all components associated with path tracing control from timing analysis. |
get | Extracts values for the specified property. |
new | Creates new analysis for currently active design. |
properties | Gives information on command properties. |
reset | Resets all path filters to their default values. |
run | Runs analysis process and creates timing, net or timegroup report. |
save_as | Saves report or settings to file. |
set | Sets the specified property to a specified value. |
set_constraint | Sets a constraint for custom analysis. |
set_endpoints | Sets path endpoints for custom analysis. |
set_filter | Sets or removes filter constraints for timing analysis. |
set_query | Sets nets or timegroups for detailed nets or timegroup report. |
show_settings | Creates a settings report for analysis. |
各命令具体格式和参数含义用法从略。。。
推荐学习
文档程序:Xilinx ISE Help/Software Help/Timing Analyzer Help
tcl参考书:Tcl/Tk入门经典
ise约束编写文档:ISE中约束文件的编写
Timing_Analyzer学习记录