1 module handshake( 2 input clka,wra_n,da,clkb,rst, 3 output reg [7:0] db, 4 output reg wrb_n 5 ); 6  7 reg ack,temp,req1; 8 reg [7:0] data; 9 always@(posedge clka or negedge rst)10 if(!rst)11     data<=8‘d0;12 else if(!wra_n)13     data<={data[6:0],da};//data<={da,data[7:1]}；14 always@(posedge clkb or negedge rst)15 if(!rst)16     begin17     req1<=1‘b1;18     temp<=1‘b1;19     end20 else 21     begin22     temp<=wra_n;23     req1<=temp;24     end25 assign wra_n_rising=temp&&(~req1);//捕获wra_n的上升沿，使能wrb_n一个时钟周期26 always@(posedge clkb or negedge rst)27 if(wra_n_rising)28 begin29 wrb_n<=1‘b1;30 db<=data;31 end32 else33 begin34 wrb_n<=1‘b0;35 db<=8‘hxx;36 end37 endmodule