3 registers for starting pos:

LDTR, GDTR( register for starting addr of DT)

---段描述符
每个段由一个8字节（64位）的段描述符来描述，他表示段的各项属性。段描述符放在叫全局描述符表（Global Descriptor Table：GDT )或局部描述符表（Local Descriptor Table：LDT）中。GDT和LDT可以理解为数组。而段选择符里的索引是用于选择在这个数组当中的元素。
如：GDT[index],表示GDT中第index个段描述符。

CPU当中有两个特殊控制器gdtr和ldtr分别存储GDT和LDT的地址

CR3(control register for starting addr of Page directory)

 内核先将当前任务的页目录表的物理地址填入cr3寄存器。

Descriptor table structure:

Base address: A 32-bit integer that defines the starting location of the segment in the 4 GByte
linear address space.
Privilege level: Each segment can be assigned a privilege level between 0 and 3, where 0 is the
most privileged, usually for operating system kernel code. If a program with a higher-numbered
privilege level tries to access a segment having a lower-numbered privilege level, a processor fault
is generated.
Segment type: Indicates the type of segment and specifies the type of access that can be made
to the segment and the direction the segment can grow (up or down). Data (including Stack) segments
can be read-only or read/write and can grow either up or down. Code segments can be
execute-only or execute/read-only.
Segment present flag: This bit indicates whether the segment is currently present in physical
memory.
Granularity flag: Determines the interpretation of the Segment limit field. If the bit is clear,
the segment limit is interpreted in byte units. If the bit is set, the segment limit is interpreted in
4096-byte units.
Segment limit: This 20-bit integer specifies the size of the segment. It is interpreted in one of
the following two ways, depending on the Granularity flag:
• The number of bytes in the segment, ranging from 1 to 1 MByte.
• The number of 4096-byte units, permitting the segment size to range from 4 KByte to 4 GByte.

Descriptor table structure:

Page directory: An array of up to 1024 32-bit page-directory entries.
• Page table: An array of up to 1024 32-bit page-table entries.
• Page: A 4 KByte or 4 MByte address space.
To simplify the following discussion, we will assume that 4 KByte pages are used:
A linear address is divided into three fields: a pointer to a page-directory entry, a pointer to a
page-table entry, and an offset into a page frame. Control register (CR3) contains the starting
address of the page directory. The following steps are carried out by the processor when translating
a linear address to a physical address, as shown in Figure 11–9:
1. The linear address references a location in the linear address space.
2. The 10-bit directory field in the linear address is an index to a page-directory entry. The pagedirectory
entry contains the base address of a page table.
3. The 10-bit table field in the linear address is an index into the page table identified by the
page-directory entry. The page-table entry at that position contains the base location of a page
in physical memory.
4. The 12-bit offset field in the linear address is added

下面来源：

Linear adress and physical address

Linear address is generated after page table mapping. Physical addres is generated before page table mapping(ie paging).

Linear Adress,created by adding logical address to the base of segment, CS,DS,ES,SS,FSor GS.

When Paging is enabled, the page tables are used to translate linear address to physical address.

On the Other Hand, Physical Address is nothing but, the address value that appears on pins of processor during a memory read/memory write operations.

InShort, we can say if paging is disabled linear address = physical address

Logical Address->Linear Address->Physical Address