首页 > 代码库 > Verilog之case语句

Verilog之case语句

verilog设计进阶

时间:201456日星期二

 

主要收获:

1. 学会使用case语句;

2. 学会使用随机函数$random

 

$random

1. 函数说明:$random函数调用时返回一个32位的随机数,它是一个带符号的整形数。

2. 产生0~59之间的随机数的例子:

reg[23:0] rand;

rand={$random} % 60;

3. 产生一个在min, max之间随机数的例子:

reg[23:0] rand;

rand = min+{$random}%(max-min+1);

(摘自昔如烟的博客)

 

Verilog程序:

module alu(out, opcode, a, b);

    output[7:0]    out;

    reg[7:0]    out;

    input[2:0]    opcode;

    input[7:0]    a, b;

    

    always@(opcode or a or b) begin

        case(opcode)

            `plus:    out = a + b;

            `minus:    out = a - b;

            `band:    out = a & b;

            `bor:    out = a | b;

            `unegate:out= ~a;

            default: out = 8‘hx;

        endcase

    end

endmodule

 

测试程序:

`timescale 1ns/1ns

 

module alutest;

    wire[7:0] out;

    reg [7:0] a, b;

    reg [2:0] opcode;

    parameter times = 5;

    

    initial begin

        a={$random}%256;

        b={$random}%256;

        opcode=3‘d0;

        repeat(times) begin

            #100;

            a={$random}%256;

            b={$random}%256;

            opcode=opcode+1;

        end

        #100 $stop;

    end

    

    alu u1(out, opcode, a, b);

endmodule

 

仿真波形: