首页 > 代码库 > UVM基础之------uvm_port_base
UVM基础之------uvm_port_base
Port Base Classes
uvm_port_component_base This class defines an interface for obtaining a port’s connectivity lists after or during the end_of_elaboration phase.主要用来在end_of_elaboration phase后返回某个接口的连接列表
uvm_port_component #(PORT) See description of uvm_port_component_base for information about this class是对uvm_port_component_base的特化，实现uvm_port_component_base中的接口
uvm_port_base #(IF) Transaction-level communication between components is handled via its ports, exports, and imps, all of which derive from this class.是ports,exports,imps的基类，里边实例化了uvm_port_component #(PORT)
typedef uvm_port_component_base uvm_port_list[string];//定义了一个uvm_port_component_base 的数组类型uvm_port_list
uvm_port_component_base://这是一个纯虚类，定义的是纯虚方法，继承自这个类的子类需要提供纯虚方法的实现。
1. 这个类定义了一个接口在end_of_elaboration后获取一个端口的连接列表，The sub-class, uvm_port_component #(PORT), implements this interface.
2. The connectivity lists are returned in the form of handles to objects of this type. This allowing traversal of any port’s fan-out and fan-in network through recursive calls to get_connected_to and get_provided_to. Each port’s full name and type name can be retrieved using get_full_name and get_type_name methods inherited from uvm_component.
3. 内部实现的接口
3.1 pure virtual function void get_connected_to(ref uvm_port_list list);该port被连接到了那些port, export,implementations,通过uvm_port_list 返回
1. For a port or export type, this function fills list with all of the ports, exports and implementations that this port is connected to.
3.2 pure virtual function void get_provided_to(ref uvm_port_list list);//本export,implementation为那些port,export,implementation提供了实现
2. For an implementation or export type, this function fills list with all of the ports, exports and implementations that this port is provides its implementation to.
3.3 pure virtual function bit is_port();//根据本port的类型返回
3.4 pure virtual function bit is_export();
3.5 pure virtual function bit is_imp();
剖析uvm_port_component #(PORT)扩展自uvm_port_component_base
2.1 唯一属性PORT m_port;
2.2 function new (string name, uvm_component parent, PORT port);给m_port=port
2.3 virtual function string get_type_name()返回port的类型名字
2.4 virtual function void resolve_bindings();出来m_port的所有端口链接
2.5 function PORT get_port();返回m_port,下列函数都是调用m_port的对应函数实现
2.6 virtual function void get_connected_to(ref uvm_port_list list);//返回实际的端口目标m_port的连接数
2.7 virtual function void get_provided_to(ref uvm_port_list list)//返回实际的端口目标m_port的连接数
2.8 function bit is_port ();
2.9 function bit is_export ();
2.10 function bit is_imp ();
uvm_port_base #(IF)该类继承了IF并在内部组合了uvm_port_component #(PORT＝IF)而这些构成了tlm中各种接口的基类.所以uvm_port_base #(IF)是uvm_port_component #(PORT＝IF)的代理
1. 组建之间的Transaction-level 通信是通过组件的ports，exports及imps，这些都是由这个类继承而来。
2. IF The interface type implemented by the subtype to this base port，For the TLM interfaces, the IF
parameter is always uvm_tlm_if_base #(T1,T2).
3. Just before uvm_component::end_of_elaboration_phase, an internal uvm_component::resolve_bindings process occurs，after which each port and export
holds a list of all imps connected to it via hierarchical connections to other ports and exports
4. uvm_port_base拥有组件的属性,他们有一个层次实例路径和父母 Because SystemVerilog does not support multiple inheritance,uvm_port_base cannot extend both the interface it implements and uvm_component.Thus, uvm_port_base contains a local instance of uvm_component, to which it delegates
such commands as get_name, get_full_name, and get_parent.
// local, protected, and non-user properties
protected int unsigned m_if_mask;
protected this_type m_if; // REMOVE
protected int unsigned m_def_index;
uvm_port_component #(this_type) m_comp; //组合方式声明一个uvm_port_component #(PORT)
local this_type m_provided_by[string]; //连接到和被连接到的port
local this_type m_provided_to[string];
local uvm_port_type_e m_port_type;
local int m_min_size; //允许连接的最大最小端口数量
local int m_max_size;
local bit m_resolved;
local this_type m_imp_list[string];//一个实现的列表
3.1 function new (string name,
uvm_component parent,
uvm_port_type_e port_type,
int min_size=0,
int max_size=1);//配置port的类型，连接数的限制，等
1. 前面两个参数是一般的uvm_component构造类的参数
2. The port_type can be one of UVM_PORT, UVM_EXPORT, or UVM_IMPLEMENTATION.
3. The min_size and max_size specify the minimum and maximum number of implementation (imp) ports that must be connected to this port base by the end of elaboration. Setting max_size to UVM_UNBOUNDED_CONNECTIONS sets no maximum,i.e., an unlimited number of connections are allowed.
3.2 function string get_name();//m_comp.get_name()
3.3 virtual function string get_full_name();//m_comp.get_full_name()
3.4 virtual function uvm_component get_parent()//m_comp.get_parent()
3.5 virtual function uvm_port_component_base get_comp();return m_comp;
1. 返回一个代表这个端口内部代理组件的句柄
2. Ports 被认为是组件，但是他们并没有继承uvm_component，相反,它们包含uvm_port_component #(PORT)的一个实例作为这个端口的代理
3.6 virtual function string get_type_name();//返回类型名
1. Otherwise, only a generic “uvm_port”, “uvm_export” or “uvm_implementation” is returned.
3.7 function int max_size ();function int min_size ();返回大小范围值
3.8 function bit is_unbounded ();测试max_int是否无穷大，是否为－1
3.9 function bit is_port ();function bit is_export ();function bit is_imp ();测试m_port_type的类型
3.10 function int size ();//返回m_imp_list.num()，连接到本port的export,port, implementation数
1. Gets the number of implementation ports connected to this port. The value is not valid before the end_of_elaboration phase, as port connections have not yet been resolved
3.11function uvm_port_base #(IF) get_if(int index=0);//从m_imp_list返回一个uvm_port_base #(IF)
3.12 virtual function void resolve_bindings();//该函数在end_of_elaboration phase阶段前自动调用他检查每个port的fanout是否都提供了实现，并记下实现的数目和min, max做比较
3.13 function void set_if (int index=0);//取出一个实现给m_if，m_default_if
3.14 function void set_default_index (int index);
3.15 local function void m_add_list (this_type provider);把一个实现记录到m_imp_list
virtual function void connect（this type provider）；
1. Connects this port to the given provider port，必须要满足下面的条件：
1. Their type parameters must match
2. The provider’s interface type (blocking, non-blocking, analysis, etc.) must be compatible.Each port has an interface mask that encodes the interface(s) it supports. If the bitwise AND of these masks is equal to the this port’s mask, the requirement is met and the ports are compatible. For example, a uvm_blocking_put_port #(T) is compatible with a uvm_put_export #(T) and uvm_blocking_put_imp #(T) because the export and imp provide the interface
required by the uvm_blocking_put_port.
3. Ports of type UVM_EXPORT can only connect to other exports or imps.
4. Ports of type UVM_IMPLEMENTATION cannot be connected, as they are bound to the component that implements the interface at time of construction
注意：
If this port is a UVM_PORT type, the provider can be a parent port, or a sibling export or implementation port.
If this port is a UVM_EXPORT type, the provider can be a child export or implementation port.
3.16 local function bit m_check_relationship (this_type provider);对连接关系进行检查
analysis port, allow connection to anywhere
Connecting port-to-port: CHILD.port.connect(PARENT.port)
Connecting port-to-export: SIBLING.port.connect(SIBLING.export)
Connecting port-to-imp: SIBLING.port.connect(SIBLING.imp)
Connecting export-to-export: PARENT.export.connect(CHILD.export)
Connecting export-to-imp: PARENT.export.connect(CHILD.imp)
3.17 function void get_provided_to (ref uvm_port_list list); //返回m_provide_to
3.18function void get_connected_to (ref uvm_port_list list); //返回m_provided_by
3.19function void debug_provided_to (int level=0, int max_level=-1); //本函数打印一个port/export的图谱
3.20 function void debug_connected_to (int level=0, int max_level=-1); //本函数打印一个本port到port/export/implement的图谱
3.21 virtual function void connect (this_type provider);//为provider到本port提供连接会检查一些连接规则，如果连接规则违反会在这里进行告警，对这部分的连接规则：
uvm_blocking_put_port #(T)－》uvm_put_export #(T)－》uvm_blocking_put_imp #(T)
Ports of type <UVM_EXPORT> can only connect to other exports or imps
Ports of type <UVM_IMPLEMENTATION> can not be connected, as they are
bound to the component that implements the interface at time of
construction.
port is an UVM_PORT type, the ~provider~ can be a parent port,or a sibling export or implementation port
If this port is an <UVM_EXPORT> type, the provider can be a child export or implementation port
location:
来自为知笔记(Wiz)
声明：以上内容来自用户投稿及互联网公开渠道收集整理发布，本网站不拥有所有权，未作人工编辑处理，也不承担相关法律责任，若内容有误或涉及侵权可进行投诉： 投诉/举报 工作人员会在5个工作日内联系你，一经查实，本站将立刻删除涉嫌侵权内容。