/*
*this file is use to connect the dule port ram and 8731
*when the up edge of lrck,read from the ram,and when the down edge of lrck,increace the ram address
*when the up edge of bclk,shift the 64 regs,and the msb is out to the 8731 dacda pin 
*/
module data_64
(
input clk,
input rst_n,
input [31:0]q,
input bclk,
input lrck,
output q_out,
output rd_en,
output [16:0]ram_addr
);

//**************************************************************************************************
//up and down edge of lrck detect module
reg latch0;
reg latch1;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
    begin
        latch0<=1‘b0;
        latch1<=1‘b0;
    end
    else 
    begin
        latch0<=lrck;
        latch1<=latch0;
    end
end
wire up_detect;
wire down_detect;
assign up_detect=latch0 && (~latch1);
assign rd_en=up_detect;
assign down_detect=latch1 && (~latch0);

//****************************************************************************************************************
//up and down edge of bclk detect module
reg latch2;
reg latch3;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
    begin
        latch2<=1‘b0;
        latch3<=1‘b0;
    end
    else
    begin
        latch2<=bclk;
        latch3<=latch2;
    end
end
wire up;
wire down;
assign up=latch2 && (~latch3);
assign down=latch3 && (~latch2);


//************************************************************************************************************
//latch up_detect module,delay the up_detect for one clk for the data read from ram
reg write;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        write<=1‘b0;
    else
        write<=up_detect;
end

//*************************************************************************************************************
//64 reg module 
reg[31:0]data;
wire[23:0]gnd;
wire shift;
assign gnd=24‘b0;
assign shift=1‘b0;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        data<=32‘b0;
    else if(write)    
        data<=q[31:0];    
    else if(up && en)
        data<={data[30:0],shift};
end 
assign q_out=data[31];

//************************************************************************************************************
//ram addr generater
reg[16:0]addr;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        addr<=17‘b0;
    else if((addr==17‘b11111_1111_1111_1111) && (down_detect ||up_detect))
        addr<=15‘b0;
    else if(down_detect ||up_detect)
        addr<=addr+1‘b1;
end
assign ram_addr=addr; 

//************************************************************************************************************
//counter enable module
reg en;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        en<=1‘b0;
    else if(cnt_over)
        en<=1‘b0;
    else if(up_detect || down_detect)
        en<=1‘b1;
end
//*************************************************************************************************************
//16 bits counter,count the BCLK posedge
reg[7:0]cnt;
wire cnt_over;
wire not_over;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
    begin
        cnt<=8‘b0;
//        cnt_over<=1‘b0;
    end
    else if((cnt==8‘d16) && en )
    begin
        cnt<=8‘b0;
//        cnt_over<=1‘b1;
    end 
    else if(en && up)
    begin
        cnt<=cnt+1‘b1;
//        cnt_over<=1‘b0;
    end
end
assign cnt_over=(cnt==8‘d16)?1‘b1:1‘b0;
assign not_over=~cnt_over;

endmodule 

module wr_req_detect
(
input clk,
input rst_n,
input wr_req,
output wr_req_detect
);
reg latch0;
reg latch1;
reg latch2;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
    begin
        latch0<=1‘b0;
        latch1<=1‘b0;
        latch2<=1‘b0;
    end
    else 
    begin
        latch0<=wr_req;
        latch1<=latch0;
        latch2<=latch1;
    end
end
assign wr_req_detect=latch0 && (~latch1);
endmodule 

/*
 * sopc.h
 *
 *  Created on: 2011-8-10
 *      Author: Fu-xiaoliang
 */

#ifndef SOPC_H_
#define SOPC_H_
#include "system.h"
#define _LED
typedef struct
{
    unsigned long int DATA;
    unsigned long int DIRECTION;
    unsigned long int INTERRUPT_MASK;
    unsigned long int EDGE_CAPTURE;
}PIO_STR;
#ifdef _LED
#define SD_DA ((PIO_STR *)SD_DA_BASE)
#define SD_CMD ((PIO_STR *)SD_CMD_BASE)
#define SD_CS ((PIO_STR *)SD_CS_N_BASE)
#define SD_CLK ((PIO_STR *)SD_CLK_BASE)
#define WR_ADDR ((PIO_STR *)WR_ADDR_BASE)
#define WR_CLK ((PIO_STR *)WR_CLK_BASE)
#define WR_DAT ((PIO_STR *)WR_DAT_BASE)
#define WR_EN ((PIO_STR *)WR_EN_BASE)
#define WR_USE_W ((PIO_STR *)WR_USE_W_BASE)
#define RD_EN ((PIO_STR *)RD_EN_BASE)
#define I2C_DAT ((PIO_STR *)I2C_DAT_BASE)
#define I2C_SCLK ((PIO_STR *)I2C_SCLK_BASE)
#define LED ((PIO_STR *)LED_BASE)
#define _SD
#endif

#ifdef _SD
#define data (SD_DA->DATA)
#define cmd (SD_CMD->DATA)
#define cs (SD_CS->DATA)
#define clk (SD_CLK->DATA)
#endif
#define uc unsigned char
#endif /* SOPC_H_ */