1 #ifdef NIOS2_MMU_PRESENT 2 /* Convert KERNEL region address to IO region address */ 3 #define BYPASS_DCACHE_MASK   (0x1 << 29) 4 #else 5 /* Set bit 31 of address to bypass D-cache */ 6 #define BYPASS_DCACHE_MASK   (0x1 << 31) 7 #endif 8  9 /*10  * Convert a pointer to a block of cached memory, into a block of11  * uncached memory.12  */13 14 volatile void* alt_remap_uncached (void* ptr, alt_u32 len)15 {16   alt_dcache_flush (ptr, len);17   return (volatile void*) (((alt_u32) ptr) | BYPASS_DCACHE_MASK);18 }

 1 #ifdef NIOS2_FLUSHDA_SUPPORTED 2 #define ALT_FLUSH_DATA(i) __asm__ volatile ("flushda (%0)" :: "r" (i)); 3 #else 4 #define ALT_FLUSH_DATA(i) __asm__ volatile ("flushd (%0)" :: "r" (i)); 5 #endif /* NIOS2_FLUSHDA_SUPPORTED */ 6  7 /* 8  * alt_dcache_flush() is called to flush the data cache for a memory 9  * region of length "len" bytes, starting at address "start".10  *11  * Any dirty lines in the data cache are written back to memory.12  */13 14 void alt_dcache_flush (void* start, alt_u32 len)15 {16 #if NIOS2_DCACHE_SIZE > 017 18   char* i;19   char* end; 20 21   /*22    * This is the most we would ever need to flush.23    *24    * SPR 196942, 2006.01.13: The cache flush loop below will use the25    * ‘flushda‘ instruction if its available; in that case each line26    * must be flushed individually, and thus ‘len‘ cannot be trimmed.27    */28   #ifndef NIOS2_FLUSHDA_SUPPORTED29   if (len > NIOS2_DCACHE_SIZE)30   {31     len = NIOS2_DCACHE_SIZE;32   }33   #endif34 35   end = ((char*) start) + len; 36 37   for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE)38   { 39     ALT_FLUSH_DATA(i); 40   }41 42   /* 43    * For an unaligned flush request, we‘ve got one more line left.44    * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a 45    * multiple of 2 (which it always is).46    */47 48   if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1))49   {50     ALT_FLUSH_DATA(i);51   }52 53 #endif /* NIOS2_DCACHE_SIZE > 0 */54 }