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ARM architectures

2024-07-22 08:31:30   226人阅读

https://gitorious.org/freebsd/freebsd/raw/56c5165837bf08f50ca4a08c6b2da91f73852960:sys/arm/include/acle-compat.h

/* * Copyright (c) 2014 ARM Ltd * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright *    notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright *    notice, this list of conditions and the following disclaimer in the *    documentation and/or other materials provided with the distribution. * 3. The name of the company may not be used to endorse or promote *    products derived from this software without specific prior written *    permission. * * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS‘‘ AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */#ifndef __ARM_ARCH/* ACLE standardises a set of pre-defines that describe the ARM architecture.   These were mostly implemented in GCC around GCC-4.8; older versions   have no, or only partial support.  To provide a level of backwards   compatibility we try to work out what the definitions should be, given   the older pre-defines that GCC did produce.  This isn‘t complete, but   it should be enough for use by routines that depend on this header.  *//* No need to handle ARMv8, GCC had ACLE support before that.  */#define __ARM_ACLE 101# ifdef __ARM_ARCH_7__/* The common subset of ARMv7 in all profiles.  */#  define __ARM_ARCH 7#  define __ARM_ARCH_ISA_THUMB 2#  define __ARM_FEATURE_CLZ#  define __ARM_FEATURE_LDREX 7#  define __ARM_FEATURE_UNALIGNED# endif# if defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__)#  define __ARM_ARCH 7#  define __ARM_ARCH_ISA_THUMB 2#  define __ARM_ARCH_ISA_ARM#  define __ARM_FEATURE_CLZ#  define __ARM_FEATURE_SIMD32#  define __ARM_FEATURE_DSP#  define __ARM_FEATURE_QBIT#  define __ARM_FEATURE_SAT#  define __ARM_FEATURE_LDREX 15#  define __ARM_FEATURE_UNALIGNED#  ifdef __ARM_ARCH_7A__#   define __ARM_ARCH_PROFILE ‘A‘#  else#   define __ARM_ARCH_PROFILE ‘R‘#  endif# endif# ifdef __ARM_ARCH_7EM__#  define __ARM_ARCH 7#  define __ARM_ARCH_ISA_THUMB 2#  define __ARM_FEATURE_CLZ#  define __ARM_FEATURE_SIMD32#  define __ARM_FEATURE_DSP#  define __ARM_FEATURE_QBIT#  define __ARM_FEATURE_SAT#  define __ARM_FEATURE_LDREX 7#  define __ARM_FEATURE_UNALIGNED#  define __ARM_ARCH_PROFILE ‘M‘# endif# ifdef __ARM_ARCH_7M__#  define __ARM_ARCH 7#  define __ARM_ARCH_ISA_THUMB 2#  define __ARM_FEATURE_CLZ#  define __ARM_FEATURE_QBIT#  define __ARM_FEATURE_SAT#  define __ARM_FEATURE_LDREX 7#  define __ARM_FEATURE_UNALIGNED#  define __ARM_ARCH_PROFILE ‘M‘# endif# ifdef __ARM_ARCH_6T2__#  define __ARM_ARCH 6#  define __ARM_ARCH_ISA_THUMB 2#  define __ARM_ARCH_ISA_ARM#  define __ARM_FEATURE_CLZ#  define __ARM_FEATURE_SIMD32#  define __ARM_FEATURE_DSP#  define __ARM_FEATURE_QBIT#  define __ARM_FEATURE_SAT#  define __ARM_FEATURE_LDREX 4#  define __ARM_FEATURE_UNALIGNED# endif# ifdef __ARM_ARCH_6M__#  define __ARM_ARCH 6#  define __ARM_ARCH_ISA_THUMB 1#  define __ARM_ARCH_PROFILE ‘M‘# endif# if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__)   || defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__)   || defined (__ARM_ARCH_6ZK__)#  define __ARM_ARCH 6#  define __ARM_ARCH_ISA_THUMB 1#  define __ARM_ARCH_ISA_ARM#  define __ARM_FEATURE_CLZ#  define __ARM_FEATURE_SIMD32#  define __ARM_FEATURE_DSP#  define __ARM_FEATURE_QBIT#  define __ARM_FEATURE_SAT#  define __ARM_FEATURE_UNALIGNED#  ifndef __thumb__#   if defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6ZK__)#    define __ARM_FEATURE_LDREX 15#   else#    define __ARM_FEATURE_LDREX 4#   endif#  endif# endif# if defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5E__)#  define __ARM_ARCH 5#  define __ARM_ARCH_ISA_ARM#  ifdef __ARM_ARCH_5TE__#   define __ARM_ARCH_ISA_THUMB 1#  endif#  define __ARM_FEATURE_CLZ#  define __ARM_FEATURE_DSP# endif# if defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5__)#  define __ARM_ARCH 5#  define __ARM_ARCH_ISA_ARM#  ifdef __ARM_ARCH_5TE__#   define __ARM_ARCH_ISA_THUMB 1#  endif#  define __ARM_FEATURE_CLZ# endif# ifdef __ARM_ARCH_4T__#  define __ARM_ARCH 4#  define __ARM_ARCH_ISA_ARM#  define __ARM_ARCH_ISA_THUMB 1# endif# ifdef __ARM_ARCH_4__#  define __ARM_ARCH 4#  define __ARM_ARCH_ISA_ARM# endif# if defined (__ARM_ARCH_3__) || defined (__ARM_ARCH_3M__)#  define __ARM_ARCH 3#  define __ARM_ARCH_ISA_ARM# endif# ifdef __ARM_ARCH_2__#  define __ARM_ARCH 2#  define __ARM_ARCH_ISA_ARM# endif# ifdef __ARMEB__#  define __ARM_BIG_ENDIAN# endif/* If we still don‘t know what the target architecture is, then we‘re   probably not using GCC.  */# ifndef __ARM_ARCH#  error Unable to determine architecture version.# endif#endif /* __ARM_ARCH  */

http://en.wikipedia.org/wiki/ARM_architecture

 

ArchitectureBit
width		Cores designed by ARM HoldingsCores designed by third partiesCortex profileReferences
ARMv1
32/26
ARM1   
ARMv2
32/26
ARM2, ARM3Amber, STORM Open Soft Core[28]  
ARMv3
32
ARM6, ARM7   
ARMv4
32
ARM8StrongARM, FA526  
ARMv4T
32
ARM7TDMI, ARM9TDMI   
ARMv5
32
ARM7EJ, ARM9E, ARM10EXScale, FA626TE, Feroceon, PJ1/Mohawk  
ARMv6
32
ARM11   
ARMv6-M
32
ARM Cortex-M0, ARM Cortex-M0+, ARM Cortex-M1 Microcontroller 
ARMv7-M
32
ARM Cortex-M3 
Microcontroller
 
ARMv7E-M
32
ARM Cortex-M4 
Microcontroller
 
ARMv7-R
32
ARM Cortex-R4, ARM Cortex-R5, ARM Cortex-R7 
Real-time
 
ARMv7-A
32
ARM Cortex-A5, ARM Cortex-A7, ARM Cortex-A8, ARM Cortex-A9, ARM Cortex-A12, ARM Cortex-A15, ARM Cortex-A17Krait, Scorpion, PJ4/Sheeva, Apple A6/A6X (Swift)
Application
 
ARMv8-A
64/32
ARM Cortex-A53, ARM Cortex-A57[29]X-Gene, Denver, Apple A7 (Cyclone), AMD K12
Application
[30][31]
ARMv8-R
32
No announcements yet 
Real-time
[32][33]

A list of vendors who implement ARM cores in their design (application specific standard products (ASSP), microprocessor and microcontrollers) is provided by ARM Holdings.[34]

 

Designed by ARM[edit]

ARM familyARM architectureARM coreFeatureCache (I / D),MMUTypical MIPS @MHz
ARM1ARMv1ARM1First implementationNone 
ARM2ARMv2ARM2ARMv2 added the MUL (multiply) instructionNone4 MIPS @ 8 MHz
0.33 DMIPS/MHz
ARMv2aARM250Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructionsNone, MEMC1a7 MIPS @ 12 MHz
ARM3ARMv2aARM3First integrated memory cache4 KB unified12 MIPS @ 25 MHz
0.50 DMIPS/MHz
ARM6ARMv3ARM60ARMv3 first to support 32-bit memory address space (previously 26-bit)None10 MIPS @ 12 MHz
ARM600As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)4 KB unified28 MIPS @ 33 MHz
ARM610As ARM60, cache, no coprocessor bus4 KB unified17 MIPS @ 20 MHz
0.65 DMIPS/MHz
ARM7ARMv3ARM700 8 KB unified40 MHz
ARM710As ARM700, no coprocessor bus8 KB unified40 MHz
ARM710aAs ARM7108 KB unified40 MHz
0.68 DMIPS/MHz
ARM7TDMIARMv4TARM7TDMI(-S)3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM26-bit addressingNone15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz
ARM710TAs ARM7TDMI, cache8 KB unified, MMU36 MIPS @ 40 MHz
ARM720TAs ARM7TDMI, cache8 KB unified, MMU with FCSE (Fast Context Switch Extension)60 MIPS @ 59.8 MHz
ARM740TAs ARM7TDMI, cacheMPU 
ARM7EJARMv5TEJARM7EJ-S5-stage pipeline, Thumb, Jazelle DBX, Enhanced DSP instructionsNone 
ARM8ARMv4ARM810[4][5]5-stage pipeline, static branch prediction, double-bandwidth memory8 KB unified, MMU84 MIPS @ 72 MHz
1.16 DMIPS/MHz
ARM9TDMIARMv4TARM9TDMI5-stage pipeline, ThumbNone 
ARM920TAs ARM9TDMI, cache16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension)[6]200 MIPS @ 180 MHz
ARM922TAs ARM9TDMI, caches8 KB / 8 KB, MMU 
ARM940TAs ARM9TDMI, caches4 KB / 4 KB, MPU 
ARM9EARMv5TEARM946E-SThumb, Enhanced DSP instructions, cachesVariable, tightly coupled memories, MPU 
ARM966E-SThumb, Enhanced DSP instructionsNo cache, TCMs 
ARM968E-SAs ARM966E-SNo cache, TCMs 
ARMv5TEJARM926EJ-SThumb, Jazelle DBX, Enhanced DSP instructionsVariable, TCMs, MMU220 MIPS @ 200 MHz
ARMv5TEARM996HSClockless processor, as ARM966E-SNo caches, TCMs, MPU 
ARM10EARMv5TEARM1020E6-stage pipeline, Thumb, Enhanced DSP instructions, (VFP)32 KB / 32 KB, MMU 
ARM1022EAs ARM1020E16 KB / 16 KB, MMU 
ARMv5TEJARM1026EJ-SThumb, Jazelle DBX, Enhanced DSP instructions, (VFP)Variable, MMU or MPU 
ARM11ARMv6ARM1136J(F)-S[7]8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), Enhanced DSP instructionsVariable, MMU740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz
ARMv6T2ARM1156T2(F)-S8-stage pipeline, SIMD, Thumb-2, (VFP), Enhanced DSP instructionsVariable, MPU 
ARMv6ZARM1176JZ(F)-SAs ARM1136EJ(F)-SVariable, MMU + TrustZone965 DMIPS @ 772 MHz, up to 2,600 DMIPS with four processors[8]
ARMv6KARM11 MPCoreAs ARM1136EJ(F)-S, 1–4 core SMPVariable, MMU 
SecurCoreARMv6-MSC000  0.9 DMIPS/MHz
ARMv4TSC100   
ARMv7-MSC300  1.25 DMIPS/MHz
Cortex-MARMv6-MCortex-M0[9]Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryOptional cache, no TCM, no MPU0.84 DMIPS/MHz
Cortex-M0+[11]Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions0.93 DMIPS/MHz
Cortex-M1[12]Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memoryOptional cache, 0-1024 KB I-TCM, 0-1024 KB D-TCM, no MPU136 DMIPS @ 170 MHz,[13](0.8 DMIPS/MHz FPGA-dependent)[14]
ARMv7-MCortex-M3[15]Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions1.25 DMIPS/MHz
ARMv7E-MCortex-M4[16]Microcontroller profile, Thumb / Thumb-2 / DSP / optional FPv4 single-precision FPU, hardware multiply and divide instructions, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions1.25 DMIPS/MHz
Cortex-RARMv7-RCortex-R4[17]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstepwith fault logic0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt MPU with 8/12 regions 
Cortex-R5 (MPCore)[18]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP)[19]0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt MPU with 12/16 regions 
Cortex-R7 (MPCore)[20]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP[19]0–64 KB / 0–64 KB, ? of 0–128 KB TCM, opt MPU with 16 regions 
Cortex-AARMv7-ACortex-A5[21]Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)4-64 KB / 4-64 KB L1, MMU + TrustZone1.57 DMIPS/MHz per core
Cortex-A7 MPCore[22]Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4-D16 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, architecture and feature set are identical to A15, 8-10 stage pipeline, low-power design[23]32 KB / 32 KB L1, 0–4 MB L2, MMU + TrustZone1.9 DMIPS/MHz per core
Cortex-A8[24]Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalarpipeline16-32 KB / 16–32 KB L1, 0–1 MB L2 opt ECC, MMU + TrustZoneUp to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)
Cortex-A9 MPCore[25]Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)16–64 KB / 16–64 KB L1, 0–8 MB L2 opt parity, MMU + TrustZone2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC40G (dual-core)
Cortex-A12[26]Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)32-64 KB / 32 KB L1, 256 KB-8 MB L23.0 DMIPS/MHz per core
Cortex-A15 MPCore[27]Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Integer divide / Fused MAC / Jazelle RCT / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline[23]32 KB w/parity / 32 KB w/ECCL1, 0–4 MB L2, L2 has ECC, MMU + TrustZoneAt least 3.5 DMIPS/MHz per core (up to 4.01 DMIPS/MHz depending on implementation)[28]
Cortex-A17 MPCoreApplication profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Integer divide / Fused MAC / Jazelle RCT / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACPMMU + TrustZone 
Cortex-A50ARMv8-ACortex-A53[29]Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline8-64 KB w/parity / 8-64 KB w/ECC L1 per core, 128 KB-2 MB L2 shared, 40-bit physical addresses2.3 DMIPS/MHz
Cortex-A57[30]Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, multi-issue, deeply out-of-order pipeline48 KB w/DED parity / 32 KB w/ECC L1 per core, 512 KB-2 MB L2 shared, 44-bit physical addressesAt least 4.1 DMIPS/MHz per core (up to 4.76 DMIPS/MHz depending on implementation)
ARM familyARM architectureARM coreFeatureCache (I / D),MMUTypical MIPS @ MHz

Designed by third parties[edit]

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

FamilyInstruction setMicroarchitectureFeatureCache (I / D), MMUTypical MIPS @ MHz
StrongARMARMv4SA-1105-stage pipeline16 KB / 16 KB, MMU100–206 MHz
1.0 DMIPS/MHz
SA-1100derivative of the SA-11016 KB / 8 KB, MMU 
Faraday[31]ARMv4FA5106-stage pipelineUp to 32 KB / 32 KB cache, MPU1.26 DMIPS/MHz
100–200 MHz
FA526Up to 32 KB / 32 KB cache, MMU1.26 MIPS/MHz
166-300 MHz
FA6268-stage pipeline32 KB / 32 KB cache, MMU1.35 DMIPS/MHz
500 MHz
ARMv5TEFA606TE5-stage pipelineNo cache, no MMU1.22 DMIPS/MHz
200 MHz
FA626TE8-stage pipeline32 KB / 32 KB cache, MMU1.43 MIPS/MHz
800 MHz
FMP626TE8-stage pipeline, SMP1.43 MIPS/MHz
500 MHz
FA726TE13 stage pipeline, dual issue2.4 DMIPS/MHz
1000 MHz
XScaleARMv5TEXScale7-stage pipeline, Thumb, Enhanced DSP instructions32 KB / 32 KB, MMU133–400 MHz
BulverdeWireless MMX, Wireless SpeedStep added32 KB / 32 KB, MMU312–624 MHz
Monahans[32]Wireless MMX2 added32 KB / 32 KB (L1), optional L2 cache up to 512 KB, MMUUp to 1.25 GHz
MarvellSheevaARMv5Feroceon5-8 stage pipeline, single-issue16 KB / 16 KB, MMU600–2000 MHz
Jolteon5-8 stage pipeline, dual-issue32 KB / 32 KB, MMU
PJ1 (Mohawk)5-8 stage pipeline, single-issue, Wireless MMX232 KB / 32 KB, MMU1.46 DMIPS/MHz
1.06 GHz
ARMv6 / ARMv7-APJ46-9 stage pipeline, dual-issue, Wireless MMX2, SMP32 KB / 32 KB, MMU2.41 DMIPS/MHz
1.6 GHz
SnapdragonARMv7-AScorpion[33]1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide)256 KB L2 per core2.1 DMIPS/MHz per core
Krait[33]1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide)4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core3.3 DMIPS/MHz per core
Apple A6,
Apple A6X		ARMv7-ASwift[34]2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEONL1: 32 KB / 32 KB, L2: 1 MB3.5 DMIPS/MHz per core
Apple A7ARMv8-ACyclone2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone /AArch64L1: 64 KB / 64 KB, L2: 1 MB1.3 GHz
Apple A8ARMv8-ACyclone gen 22 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone /AArch64L1: (unknown);KB, L2: (unknown);MB1.4 GHz
X-GeneARMv8-AX-Gene64-bit, quad issue, SMP, 64 cores[35]Cache, MMU, virtualization3 GHz
DenverARMv8-ADenver64-bit128 KB I / 64 KB DUp to 2.5 GHz
ThunderXARMv8-AThunderX8-16 / 24-48 cores (×2 w/two chips). 64-bit Up to 2.5 GHz

ARM core timeline[edit]

The following table lists each core by the year it was announced.[36][37]

YearClassic coresCortex cores
ARM7ARM8ARM 9ARM10ARM11EmbeddedReal-timeApplication
1996 ARM810    
1997  ARM9TDMI  
1998ARM7TDMI(-S)    
1999     
2000     
2001     
2002    ARM1136J(F)-S
2003  ARM966E-S
ARM968E-S		 ARM1156T2(F)-S
ARM1176JZ(F)-S
2004     Cortex-M3  
2005       Cortex-A8
2006  ARM996HS     
2007     Cortex-M1 Cortex-A9
2008        
2009     Cortex-M0 Cortex-A5
2010     Cortex-M4 Cortex-A15
2011      Cortex-R4
Cortex-R5
Cortex-R7		Cortex-A7
2012     Cortex-M0+ Cortex-A53
Cortex-A57
2013       Cortex-A12
2014       Cortex-A17

ARM architectures


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