此文章为原创出自 V3学院 www.v3edu.org,FPGA培训专家
测试激励模块 tb_hamming_12_8.V
//功能描述:给被测模块提供时钟激励,并统计解码后数据的正确性
`timescale 1ns/1ns
module tb_hamming_12_8;

reg sclk;
wire [11:0] ham_o;
wire ham_ov;
wire [11:0] deham_o;
wire deham_ov;
reg [31:0] err_cnt;
reg [23:0] buff_ham_o;

initial
begin
sclk=0;
err_cnt=0;
buff_ham_o=0;
#2000000 //run 2ms
$stop;
end

always #10 sclk<=~sclk;

top top_inst(
.sclk (sclk),
.data_o (deham_o),
.data_ov (deham_ov),
.ham_o (ham_o),
.ham_ov (ham_ov)
);

always @(posedge sclk)
if(ham_ov == 1‘b1)
buff_ham_o<={buff_ham_o[12:0],ham_o};

always @(posedge sclk)
if(deham_ov ==1‘b1 && buff_ham_o[11:0] != deham_o)
err_cnt<=err_cnt+1‘b1;

always @(posedge sclk)
if(deham_ov ==1‘b1)
if(buff_ham_o[11:0] != deham_o)
$display("Error,Now error counter is %d",err_cnt+1);
else
$display("Correct, Now error counter is %d",err_cnt);
endmodule
? 噪声污染模块 add_noise.v
//功能描述:循环把输入数据的某一比特反转,模拟被噪声污染的数据
//目的:测试模块
module add_noise(
input wire sclk,
input wire rst_n,
input wire data_inv,
input wire [11:0] data_in,
output reg data_ov,
output reg [11:0] data_o,
output wire tout
);
parameter noise_cnt_end=4‘d11;
reg [3:0] noise_cnt;

always @(posedge sclk or negedge rst_n)
if(rst_n == 1‘b0)
noise_cnt<=‘d0;
else if(data_inv == 1‘b1 && noise_cnt <noise_cnt_end)
noise_cnt<=noise_cnt+1‘b1;
else if(data_inv == 1‘b1)
noise_cnt<=‘d0;

always @(posedge sclk or negedge rst_n)
if(rst_n == 1‘b0)
data_ov <= ‘d0;
else
data_ov<=data_inv;

always @(posedge sclk or negedge rst_n)
if(rst_n == 1‘b0)
data_o<=‘d0;
else if(data_inv)
case(noise_cnt)
4‘d0:data_o<={data_in[11:1],~data_in[0]};
4‘d1:data_o<={data_in[11:2],~data_in[1],data_in[0]};
4‘d2:data_o<={data_in[11:3],~data_in[2],data_in[1:0]};
4‘d3:data_o<={data_in[11:4],~data_in[3],data_in[2:0]};
4‘d4:data_o<={data_in[11:5],~data_in[4],data_in[3:0]};
4‘d5:data_o<={data_in[11:6],~data_in[5],data_in[4:0]};
4‘d6:data_o<={data_in[11:7],~data_in[6],data_in[5:0]};
4‘d7:data_o<={data_in[11:8],~data_in[7],data_in[6:0]};
4‘d8:data_o<={data_in[11:9],~data_in[8],data_in[7:0]};
4‘d9:data_o<={data_in[11:10],~data_in[9],data_in[8:0]};
4‘d10:data_o<={data_in[11:11],~data_in[10],data_in[9:0]};
4‘d11:data_o<={~data_in[11],data_in[10:0]};
default:data_o<=data_in;
endcase

endmodule
? 数据产生模块 Gen_data.v
//功能描述:循环产生模拟数据
//目的:测试
module gen_data(
input wire sclk,
input wire rst_n,
output reg data_ov,
output reg [7:0] data_o,
output wire tout
);
reg [8:0] out_cnt;
always @(posedge sclk or negedge rst_n)
if(rst_n==1‘b0)
out_cnt<=‘d0;
else
out_cnt<=out_cnt+1‘b1;

always @(posedge sclk or negedge rst_n)
if(rst_n == 1‘b0)
data_o<=‘d0;
else
data_o<=out_cnt[8:1];

always @(posedge sclk or negedge rst_n)
if(rst_n == 1‘b0)
data_ov<=‘d0;
else
data_ov<=out_cnt[0];
endmodule
? 功能顶层模块 top.v
//顶层模块
module top(
input wire sclk,
output wire ham_ov,
output wire [11:0] ham_o,
output wire [11:0] data_o,
output wire data_ov
);
reg [7:0] rst_cnt=‘d0;//初始值为0的计数器
reg rst_n=‘d0;//全局复位信号,低有效
wire gen_data_ov;
wire [7:0] gen_data_o;
wire hamming_ov;
wire [11:0] hamming_o;
wire add_noise_ov;
wire [11:0] add_noise_o;
wire dehamming_ov;
wire [11:0] dehamming_o;

//全局复位逻辑
always @(posedge sclk)
if(rst_cnt[7] != 1‘b1)
rst_cnt<=rst_cnt+1‘b1;

always @(posedge sclk)
rst_n<=rst_cnt[7];

//数据产生模块
gen_data gen_data_inst(
.sclk (sclk),
.rst_n (rst_n),
.data_ov (gen_data_ov),
.data_o (gen_data_o),
.tout ()
);
//汉明编码模块
hamming_12_8 hamming_12_8_inst(
.sclk (sclk),
.rst_n (rst_n),
.data_inv (gen_data_ov),
.data_in (gen_data_o),
.data_ov (hamming_ov),
.data_o (hamming_o),
.tout ()
);
//噪声模块
add_noise add_noise_inst(
.sclk (sclk),
.rst_n (rst_n),
.data_inv (hamming_ov),
.data_in (hamming_o),
.data_ov (add_noise_ov),
.data_o (add_noise_o),
.tout ()
);
//汉明解码模块
dehamming_12_8 dehamming_12_8_inst(
.sclk (sclk),
.rst_n (rst_n),
.data_inv (add_noise_ov),
.data_in (add_noise_o),
.data_ov (dehamming_ov),
.data_o (dehamming_o),
.tout ()
);
//信号拉到顶层输出,防止综合器优化掉内部逻辑,在测试模块中会比对纠错后的结果是否与发送的码字一致。
assign data_o=dehamming_o;
assign data_ov=dehamming_ov;
assign ham_o=hamming_o;
assign ham_ov=hamming_ov;

endmodule
? Modelsim 仿真脚本命令 run.do

clear all

.main clear
quit -sim

Create work lib

vlib work

Compile sources

vlog "tb_hamming_12_8.v"
vlog "../design/*v"

simulation entry

vsim -voptargs=+acc work.tb_hamming_12_8

wave window types

view wave
view structure
view signals

divider

add wave -noupdate -divider {Top Module}
add wave -radix hexadecimal tb_hamming_12_8/top_inst/*

add wave -noupdate -divider {Tb_hamming_12_8}
add wave -radix hexadecimal tb_hamming_12_8/*

run 2ms
此文章为原创出自 V3学院 www.v3edu.org