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来到美国后，选了微处理器课，有幸老教授是 MIT 贝尔实验室出来的，希望好好学习这门课。

零、Chapter 0

第0章 绪论

0-2 Logic Gates

1、基础逻辑门（注意记住符号）

2、三态缓冲器

三态缓冲器（Three-state buffer），又称为三态门、三态驱动器，其三态输出受到使能输出端的控制，当使能输出有效时，器件实现正常逻辑状态输出（逻辑0、逻辑1），当使能输入无效时，输出处于高阻状态，即等效于与所连的电路断开。

3、Logic Design using Gates 为什么可以用 and 做 carry

?Note that there are 4 possible outcomes when adding a pair of binary numbers

?0 + 0 = carry 0, sum 0
?0 + 1 = carry 0, sum 1
?1 + 0 = carry 0, sum 1
?1 + 1 = carry 1, sum 0

?Recall that the AND gate only outputs 1 if both inputs are true, thus it could be used to output the carry bit.

?Recall that the XOR gate only outputs 1 if and only if one of the inputs are true.

4、半加器

另一种形式

5、全加器

6、三位全加器

Application of the previous 3 Bit Adder

?Assume we want to add the binary numbers 010 and 011..

?Using the truth table shows before..

?We know that 0+1 with no carry in will result in Sum of 1 with no carry
?Also, 1+1 with no carry in will result in sum of 0 with carry out of 1 ?Finally, 0+0 with carry in will result in sum of 1 with no carry

?Result is 0101

?The take away here is that we can cascade as many full adders as we want to add as large of a pair of binary numbers as we want.

?For example a 64 bit sum would require 64 cascaded adders

0-3 Semiconductor Memory（ROM、RAM类型）

1、Internal Organization of computers

?3 major subsystems
?CPU – Central Processing Unit ?Memory ?I/O Input Output

?Connected by buses
?Data ?Address ?Control

More About the Data Bus
?Analogous to Highway
?The more lanes, the more simultaneous traffic
?The more data buses the better
?This adds to expense
?Note that we currently have 64 bit CPUs and operating systems
?The size of the data bus is related to both size and precisions of arithmetic operations

More About the Address Bus
?Every addressable device must have a unique address
?The larger the address bus, the larger number of devices which may be addressed by the CPU
?Recall that decoders are used on addressable device to establish their address.
?The number of devices which may be addressed is always equal to 2^x where x is the number of address lines.
?For example, a 16 bit address bus can access 64k of addressable memory
?This is a unidirectional bus (send only from CPU)

2、Relation of CPU to RAM and ROM

3、Memory Capacity

?This is the number of bits a memory chip can store
?Chip capacity has units of bits, Computer system capacity has units of bytes

4、Memory Organization

?Memory chips are organized into a number of locations within the IC
?Each location can hold 1, 4, 8, 16, or more bits
?The number of bits that each location will hold is equal to the number of data
pins on the chip.
?The number of locations on the chip is determined by the number of address pins on the chip say x. 2^x is the number of locations (addresses) on the chip
?Total number of bits which may be stored on the entire chip is given by 2^(address pins) times the number of data pins

Another Organization/Capacity Example

?We have a chip with 256k capacity with 8 data pins.
?The organization is 256k/8 = 32K x 8 ?The number of address lines is 15 since 2^15 = 32K

5、不同ROM类型

Different types such as:
?PROM
?EPROM
?EEPROM
?FLASH EPROM
?MASK PROM

（1）PROM (programmable ROM) and OTP

（2）EPROM (erasable programmable ROM) and UV-EPROM

（3）Some UV-EPROM Memory Chips

（4）EEPROM (electrically erasable programmable ROM)

（5）Flash Memory EPROM

（6）Mask ROM

6、不同RAM类型

3 types
?Static RAM
?Nonvolatile RAM
?Dynamic Ram

（1）SRAM (static RAM)

（2）NV-RAM (nonvolatile RAM)

（3）DRAM (dynamic RAM)

7、Memory Block Selection

?Simple Logic Gates
?Using 74LS138
?Programmable Logic such as CPLD or FPGA

详见：http://blog.csdn.net/scythe666/article/details/52428243

Using the 74LS138 3 – 8 decoder

?One of the most widely used decoders ?3 inputs A, B, and C generate 8 active low outputs Y0 to Y7, ?Each output is connected to CS of a different memory device allowing
control of 8 memory blocks
?Three additional inputs G1, G2A, and G2B may connected to an Address or Control Signal
?G2A and G2B active low ?G1 active high ?These inputs must be terminated in way or another ?These inputs enable the device

0-4 Harvard and von Neumann CPU Architectures

一、Chapter 1

四、Chapter 4

1、分支语句集合

2、CCR register

3、Show how the cpu would subtract 05from<script type="math/tex" id="MathJax-Element-1">05 from </script>43.

这个时候需要考虑到补码，43H-05H=3EH，也就是0100 0011 - 0000 0101，这个时候减去这个数相当于加上这个数的反码，0100 0011 + 1111 1011 = 0011 1110

五、Chapter 5

5-1

5-2 逻辑运算

NEG 是2的补码

5-3

本质是相减比较大小

5-4

5-5

5-6

When is the overflow flag set?
?Either of the following conditions cause V = 1
1. There is a carry from Bit 6 to Bit 7 but no carry from Bit 7
2. There is a carry from Bit 7 but no carry from Bit 6 to Bit 7

?Note in either case we do not have a carry from both