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[Verilog]任意整数(奇数,整数)分频器设计, 50%占空比
module div_clk(clk_in, divisor, clk_out);
input clk_in;input divisor;
output clk_out;
reg clk_out = 0;
wire clk_in;
reg [7 : 0] count = 0;
wire [7 : 0] divisor;
wire odd;
assign odd = divisor & 1;
always @(clk_in)
begin
if (count == 0 && clk_in)
clk_out = 1;
else if (count == ((divisor >> 1) + odd) && (odd == !clk_in))
clk_out = 0;
if (clk_in)
begin
count = count + 1;
if (count >= divisor)
count = 0;
end
end
endmodule
TestBench:
module div_tb;
reg clk_in;
wire clk_out;
initial
begin
#0 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
10 clk_in = 1;
#10 clk_in = 0;
10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
#10 clk_in = 0;
#10 clk_in = 1;
end
wire [7 : 0] divisor = 3;
div_clk dc(.clk_in(clk_in),.clk_out(clk_out), .divisor(divisor));
endmodule
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