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ADIv5.2

ADI:ARM Debug Interface,出到现在共有五代:

1)version1 and version 2:只针对ARM7TDMI和ARM9的processor;

2)version 3:只针对ARM10的processor family;

3)ADIv4:使用与所有的ARMv6 architecture;

4)ADIv5.2:针对ARMv7-A和ARMv8-A的processor;分为了Access Port(AP) architecture和Debug Port(DP) architecture

                  DP包括三类:1)JTAG-DP; 满足IEEE 1149.1的接口;

                                    2)SW-DP; 基于packet-based protocol(host-target req, target-host ack, data transfer) 

                                    3)SWJ-DP; can switch between SWD and JTAG

                  AP包括两类:1)MEM-AP(扩展到AXI/ACE); a memory-mapped resource such as a debug peripheral  

                                    2)JTAG-AP; a legacy jtag device

DP来连接外部的host,AP来访问内部的debug component registers

 

ADIv5 DAP

CoreSight components

CoreSIght debug architecture

能提供的功能包括:

1)Embedded core debug functionality,由arm core和ETM这样的module来保证

        1)modify the contents of the internal registers and the memory system;

        2)read the contents of the internal registers and the memory system;

        3)program debug events,在某个event被触发之后,processor可以由外部可控;

        4)Force the processor to enter and exit debug state;

        5)Trace program flow around programmable events;

2)System debug functionality,系统性的debug

        1)Components within an embeded SoC

              program trace

              cross-triggering mechanisms

        2)The interconnection fabric of the system

              trace access on the interconnection fabric

ADIv5.2