module    ad_ctrl(
        clk,rst_n,ad_clk,
        ad_data,value_x,value_y,q_sig,wren,r_addr,w_addr
);

input                clk;    
input                rst_n;
input        [10:0]    value_x;
input        [10:0]    value_y;
output                ad_clk;
input        [9:0]    ad_data;
output                wren;
output        [7:0]    q_sig;
output    reg    [8:0]    r_addr;
output    reg    [8:0]    w_addr;

assign        ad_clk = ~clk;




wire        [7:0]    data_sig;
assign        data_sig = ad_data[9:2];
ram_ad    ram_ad_inst (
    .clock ( clk ),
    .data ( data_sig ),
    .rdaddress ( r_addr ),
    .wraddress ( w_addr ),
    .wren ( wren ),
    .q ( q_sig )
    );

//read ram
always @(posedge clk or negedge rst_n)
    if(!rst_n)
        r_addr <= ‘d0;
    else if((value_x >= 0 && value_x < 512) && (value_y >= 0 && value_y <256))
        r_addr <= value_x[8:0];
    else 
        r_addr <= ‘d0;
//write ram
reg        [1:0]    state;
always @(posedge clk or negedge rst_n)
    if(!rst_n)begin
        w_addr <= ‘d0;
        state <= ‘d0;
    end
    else if((value_x >= 0 && value_x < 512) && (value_y >= 256 && value_y <260))begin
        case(state)
        2‘d0:begin
            if(data_sig > 128)
                state <= 1;
            else
                state <= ‘d0;
        end
        2‘d1:begin
            if(w_addr > 510)begin
                state <= ‘d0;
                w_addr <= ‘d0;
            end
            else begin
                w_addr <= w_addr + 1‘d1;
                state <= 2‘d1;
            end
        end
        default:state <= ‘d0;
        endcase
    end
    else
        w_addr <= ‘d0;
        
//wren
reg        wren_r;
always @(posedge clk or negedge rst_n)
    if(!rst_n)
        wren_r <= 1‘d0;
    else if((value_x >= 0 && value_x < 512) && (value_y >= 0 && value_y <256))
        wren_r <= 1‘d0;
    else if((value_x >= 0 && value_x < 512) && (value_y >= 256 && value_y <260))
        wren_r <= 1‘d1;
    else
        wren_r <= 1‘d0;
assign    wren = wren_r;
endmodule