1 // synthesis translate_off
 2 `timescale 1ns / 10ps
 3 // synthesis translate_on
 4 module wb_ram (
 5     input                        clk_i,
 6     input                        rst_i,
 7     
 8     // wishbone signals
 9     input                        cyc_i,
10     input                        stb_i,
11     input                        we_i,
12     input            [3:0]        sel_i,
13     input           [31:0]        adr_i,
14     input            [31:0]        dat_i,   
15     output    reg        [31:0]      dat_o,
16     output    reg                 ack_o
17 );
18 
19 parameter mem_words = 1024;
20 
21 wire [31:0]          wr_data;
22 
23 // mux for data to ram
24 assign wr_data[31:24] = sel_i[3] ? dat_i[31:24] : dat_o[31:24];
25 assign wr_data[23:16] = sel_i[2] ? dat_i[23:16] : dat_o[23:16];
26 assign wr_data[15: 8] = sel_i[1] ? dat_i[15: 8] : dat_o[15: 8];
27 assign wr_data[ 7: 0] = sel_i[0] ? dat_i[ 7: 0] : dat_o[ 7: 0];
28 
29 // ack_o
30 always @ (posedge clk_i or posedge rst_i)
31 begin
32     if(rst_i)
33         ack_o <= 1‘b0;
34     else if(ack_o)
35         ack_o <= 1‘b0;
36     else if(!ack_o & cyc_i & stb_i)
37         ack_o <= 1‘b1; 
38     else
39         ack_o <= ack_o;
40 end
41 
42 reg [31: 0] ram [0 : mem_words - 1];
43 
44 initial $readmemh("./data.txt", ram);
45 
46 always @ (negedge clk_i)
47 begin 
48     dat_o <= ram[adr_i[31:2]];
49     if (cyc_i & stb_i & we_i)
50         ram[adr_i[31:2]] <= wr_data;
51 end 
52 
53 endmodule