module m_generate (
                clock ,
                reset ,
                m_code 
                );
    input clock ,reset ;
    output m_code ; 
    
    reg  [4:0]ori_reg   ;    //original  code 
always @ (posedge clock)
    if(!reset) 
        begin 
                ori_reg  <= 5‘b10000;
        end 
    else 
        begin 
                ori_reg[4]   <=  ori_reg[3] ^ ori_reg[0] ;
                ori_reg[3:0] <=  ori_reg[4:1] ;
        end 
        
assign m_code = ori_reg[0] ;

endmodule