1 `timescale 1ps/1ps 2 module tst5_25(); 3 reg clk; 4 reg [7:0]count; 5  6 initial fork:CNT 7   clk = 0; 8   count = 5; 9   forever #5 clk = ~clk;10   forever 11   begin12     @(posedge clk)  //waitting for the rising edge of clk13     count = count + 8‘d1;14     if(count ==8‘d67)15     disable CNT;16   end17 join18 19 endmodule