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TK1 ~ 控制GPIO

2024-09-23 08:37:53   217人阅读

  首先建立个存放gpio代码的文件夹，CD到该文件夹。

git clone git://github.com/derekmolloy/boneDeviceTree/

解压后会出现几个文件

技术分享

GPIO文件夹内的SimpleGPIO.cpp和SimpleGPIO.h复制到eclipse工作空间的src文件夹下。

包含相关头文件后编写代码：

//============================================================================
// Name        : CPPT1.cpp
// Author      : Kopu
// Version     :
// Copyright   : Oh,Shit!
// Description : Hello World in C++, Ansi-style
//============================================================================
#include "stdio.h"
#include "stdlib.h"
#include <iostream>
#include "SimpleGPIO.h"
using namespace std;

const int GPIO_PU6_P58 = 166;
const int GPIO_PH1_P50 = 57;

unsigned int IO_Data=http://www.mamicode.com/0;

void delay_ms(unsigned int num)
{
  unsigned int i,j;
  for(i=num;i>0;i--)
    for(j=80000;j>0;j--);
}
int main(void)
{
    gpio_export(GPIO_PH1_P50);
    gpio_export(GPIO_PU6_P58);
    gpio_set_dir(GPIO_PH1_P50, INPUT_PIN);
    gpio_set_dir(GPIO_PU6_P58, OUTPUT_PIN);
    while(1)
    {
     gpio_get_value(GPIO_PH1_P50,&IO_Data);
     if(IO_Data)printf("1\n");
     else printf("0\n");
     gpio_set_value(GPIO_PU6_P58, HIGH);
     delay_ms(10);
     gpio_set_value(GPIO_PU6_P58, LOW);
     delay_ms(10);
    }
 return 0;
}

关于上面的gpio对应TK1上的引脚：

 

Port  sysfs filename Physical pin Notes
GPIO_PH1 gpio57 Pin 50 on J3A1  
GPIO_PU0 gpio160 Pin 40 on J3A2  
GPIO_PU1 gpio161 Pin 43 on J3A2  
GPIO_PU2 gpio162 Pin 46 on J3A2 (Disabled by default)
GPIO_PU3 gpio163 Pin 49 on J3A2  
GPIO_PU4 gpio164 Pin 52 on J3A2  
GPIO_PU5 gpio165 Pin 55 on J3A2  
GPIO_PU6 gpio166 Pin 58 on J3A2  

技术分享

 

J3A1 
Pin Signal name Tegra K1 ball Usage/description Type/dir default Associated voltage rail Tegra pad type Connector row
1 +5V_SYS n/a Main 5V from system Power - - 1
2 GND n/a Tied to common GND Ground - - 2
3 +1.8V_VDDIO n/a Main 1.8V supply from PMU switcher 5 Power - - 1
4 TS_SPI_SCK ULPI_NXT SPI clock for Touchscreen controller (if SPI used) Input +1.8V_VDDIO ST 2
5 TS_SPI_MOSI ULPI_CLK SPI MOSI for Touchscreen controller (if SPI used) Input +1.8V_VDDIO ST 1
6 TS_SPI_CS_L ULPI_STP SPI chip select for Touchscreen controller (if SPI) Input +1.8V_VDDIO ST 2
7 TS_SPI_MISO ULPI_DIR SPI MISO for Touchscreen controller (if SPI used) Output +1.8V_VDDIO ST 1
8 GND n/a Tied to common GND Ground - - 2
9 GND n/a Tied to common GND Ground - - 1
10 +3.3V_RUN_TOUCH n/a AMS PMIC LDO9 Power - - 2
11 TS_SHDN_L GPIO_PK1 Shutdown control for Touchscreen controller Input +1.8V_VDDIO CZ 1
12 TS_CLK CLK2_OUT Clock for Touchscreen controller Input +1.8V_VDDIO ST 2
13 TS_RESET_L GPIO_PK4 Reset for Touchscreen controller Input +1.8V_VDDIO CZ 1
14 GND n/a Tied to common GND Ground - - 2
15 GND n/a Tied to common GND Ground - - 1
16 +3.3V_SYS n/a Main 3.3V supply Power - - 2
17 GPIO_PK2 GPIO_PK2 Available GPIO Output +1.8V_VDDIO CZ 1
18 GEN2_I2C_SCL_3.3V GEN2_I2C_SCL 3.3V I2C IF (Pulled up to +3.3V_LP0) Input, Open Drain +3.3V_LP0 DD 2
19 +1.8V_VDDIO n/a Main 1.8V supply from PMU switcher 5 Power - - 1
20 GEN2_I2C_SDA_3.3V GEN2_I2C_SDA 3.3V I2C IF (Pulled up to +3.3V_LP0) Bidir, Open Drain   DD 2
21 GEN1_I2C_SCL GEN1_I2C_SCL 1.8V I2C (Pulled up to +1.8V_VDDIO) Input, Open Drain +1.8V_VDDIO DD 1
22 +3.3V_RUN n/a +3.3V rail that is off in LP0 Power - - 2
23 GEN1_I2C_SDA GEN1_I2C_SDA 1.8V I2C (Pulled up to +1.8V_VDDIO) Bidir, Open Drain +1.8V_VDDIO DD 1
24 EN_AVDD_LCD n/a Enable for Embedded display from PMU GPIO4 Input - - 2
25 +VDD_MUX n/a Main 12V from Jack Power     1
26 GND n/a Tied to common GND Ground - - 2
27 EN_VDD_BL DAP3_DOUT Backlight supply enable Input +1.8V_VDDIO ST 1
28 DP_AUX_P DP_AUX_P eDP AUX control interface (+) Bidir +1.05V_RUN_AVDD LVDS/DP 2
29 GND n/a Tied to common GND Ground - - 1
30 DP_AUX_N DP_AUX_N eDP AUX control interface (-) Bidir +1.05V_RUN_AVDD LVDS/DP 2
31 LVDS_TXD0_P LVDS_TXD0_P LVDS Data lane 0 (+) or eDP Data lane 2 (+) Input +1.05V_RUN_AVDD LVDS/DP 1
32 GND n/a Tied to common GND Ground - - 2
33 LVDS_TXD0_N LVDS_TXD0_N LVDS Data lane 0 (-) or eDP Data lane 2 (+) Input +1.05V_RUN_AVDD LVDS/DP 1
34 LVDS_TXD1_P LVDS_TXD1_P LVDS Data lane 1 (+) or eDP Data lane 1 (+) Input +1.05V_RUN_AVDD LVDS/DP 2
35 GND n/a Tied to common GND Ground - - 1
36 LVDS_TXD1_N LVDS_TXD1_N LVDS Data lane 1 (-) or eDP Data lane 1 (-) Input +1.05V_RUN_AVDD LVDS/DP 2
37 LVDS_TXD3_P LVDS_TXD3_P LVDS Data lane 3 (+) - Not used for eDP Input +1.05V_RUN_AVDD LVDS/DP 1
38 GND n/a Tied to common GND Ground - - 2
39 LVDS_TXD3_N LVDS_TXD3_N LVDS Data lane 3 (-) - Not used for eDP Input +1.05V_RUN_AVDD LVDS/DP 1
40 LVDS_TXD2_P LVDS_TXD2_P LVDS Data lane 2 (+) or eDP Data lane 0 (+) Input +1.05V_RUN_AVDD LVDS/DP 2
41 GND n/a Tied to common GND Ground - - 1
42 LVDS_TXD2_N LVDS_TXD2_N LVDS Data lane 2 (-) or eDP Data lane 0 (-) Input +1.05V_RUN_AVDD LVDS/DP 2
43 LVDS_TXD4_N LVDS_TXD4_N LVDS Clock lane (+) or eDP Data lane 3 (+) Input +1.05V_RUN_AVDD LVDS/DP 1
44 GND n/a Tied to common GND Ground - - 2
45 LVDS_TXD4_P LVDS_TXD4_P LVDS Clock lane (-) or eDP Data lane 3 (-) Input +1.05V_RUN_AVDD LVDS/DP 1
46 EPP_HPD DP_HPD eDP display Hot Plug Detect input Output +3.3V_LP0 ST 2
47 GND n/a Tied to common GND Ground - - 1
48 LCD_BL_EN GPIO_PH2 Backlight enable Input +1.8V_VDDIO CZ 2
49 LCD_TE KB_ROW6 Tearing Effect from embedded display (if supported) Output +1.8V_VDDIO ST 1
50 LCD_BL_PWM GPIO_PH1 Backlight PWM Input +1.8V_VDDIO CZ 2

三排的插座：

 J3A2
Pin Signal name Tegra K1 ball Usage/description Type/dir default Associated voltage rail Tegra pad type Connector row
1 +5V_SYS n/a Main 5v from system Power - - 1
2 CAM2_PWDN GPIO_PBB6 Power Down for Camera 2 input +1.8V_RUN_CAM ST 2
3 +1.05V_RUN_CAM_REAR n/a AMS PMIC LDO7 for Camera 1 Power - - 3
4 CAM2_MCLK GPIO_PBB0 Master Reference Clock for Camera 2 input +1.8V_RUN_CAM ST 1
5 CAM_RST_L GPIO_PBB3 Reset for Camera(s) input +1.8V_RUN_CAM ST 2
6 +2.8V_RUN_CAM n/a AMS PMIC LDO4 for Camera(s) Power - - 3
7 CAM2_GPIO GPIO_PCC2 GPIO for Camera 2 Bidir +1.8V_RUN_CAM ST 1
8 CAM_I2C_SDA CAM_I2C_SDA I2C Data for Camera(s) Bidir, Open Drain +1.8V_RUN_CAM DD 2
9 GND n/a Tied to common GND Ground - - 3
10 GND n/a Tied to common GND Ground - - 1
11 CAM_I2C_SCL CAM_I2C_SCL I2C Clock for Camera(s) Input, Open Drain +1.8V_RUN_CAM SS 2
12 CSI_A_CLK_P CSI_A_CLK_P CSI Clock (+) for Camera 1 Output +1.2V_GEN_AVDD CSI 3
13 CSI_E_CLK_N CSI_E_CLK_N CSI Clock (-) for Camera 2 Output +1.2V_GEN_AVDD CSI 1
14 GND n/a Tied to common GND Ground - - 2
15 CSI_A_CLK_N CSI_A_CLK_N CSI Clock (-) for Camera 1 Output +1.2V_GEN_AVDD CSI 3
16 CSI_E_CLK_P CSI_E_CLK_P CSI Clock (+) for Camera 2 Output +1.2V_GEN_AVDD CSI 1
17 CSI_E_D0_N CSI_E_D0_N CSI Data Lane 0 (-) for Camera 2 Output +1.2V_GEN_AVDD CSI 2
18 GND n/a Tied to common GND Ground - - 3
19 GND n/a Tied to common GND Ground - - 1
20 CSI_E_D0_P CSI_E_D0_P CSI Data Lane 0 (+) for Camera 2 Output +1.2V_GEN_AVDD CSI 2
21 CSI_A_D1_N CSI_A_D1_N CSI Data Lane 1 (-) for Camera 1 Output +1.2V_GEN_AVDD CSI 3
22 +1.2V_RUN_CAM_FRONT n/a AMS PMIC LDO5 for Camera 2 Power - - 1
23 GND n/a Tied to common GND Ground - - 2
24 CSI_A_D1_P CSI_A_D1_P CSI Data Lane 1 (+) for Camera 1 Output +1.2V_GEN_AVDD CSI 3
25 +2.8V_RUN_CAM_AF n/a AMS PMIC LDO10 for Camera 1 Power +1.2V_GEN_AVDD CSI 1
26 +1.8v_VDDIO n/a AMS Switcher 5 Power - - 2
27 GND n/a Tied to common GND Ground - - 3
28 +1.8V_GEN_AVDD n/a AMS PMIC LDO2, used to sync HSIC rails Power - - 1
29 +1.8V_RUN_CAM n/a AMS PMIC LDO1 Power - - 2
30 CSI_A_D0_N CSI_A_D0_N CSI Data Lane 0 (-) for Camera 1 Output +1.2V_GEN_AVDD CSI 3
31 HSIC1_STROBE HSIC1_STROBE HSIC Strobe Bidir +1.2V_GEN_AVDD HSIC 1
32 GND n/a Tied to common GND Ground - - 2
33 CSI_A_D0_P CSI_A_D0_P CSI Data Lane 0 (+) for Camera 1 Output +1.2V_GEN_AVDD CSI 3
34 GND n/a Tied to common GND Ground - - 1
35 HSIC1_DATA HSIC1_DATA HSIC Data Bidir +1.2V_GEN_AVDD HSIC 2
36 GND n/a Tied to common GND Ground - - 3
37 +1.8V_VDDIO n/a AMS Switcher 5 Power - - 1
38 GND n/a Tied to common GND Ground - - 2
39 CSI_B_D1_N CSI_B_D1_N CSI Data Lane 3 (-) for Camera 1 Output +1.2V_GEN_AVDD CSI 3
40 GPIO_PU0 GPIO_PU0 GPIO PU0: Available for general use Bidir +1.8V_VDDIO ST 1
41 BR_UART_TXD KB_ROW9 For PM342 style Laguna FFD header Input +1.8V_VDDIO - 2
42 CSI_B_D1_P CSI_B_D1_P CSI Data Lane 3 (+) for Camera 1 Output +1.2V_GEN_AVDD - 3
43 GPIO_PU1 GPIO_PU1 GPIO PU1: Available for general use Bidir +1.8V_VDDIO ST 1
44 BR_UART1_RXD KB_ROW10 For PM342 style Laguna FFD header Output +1.8V_VDDIO - 2
45 GND n/a Tied to common GND Ground - - 3
46 GPIO_PU2 GPIO_PU2 GPIO PU2: Available for general use Bidir +1.8V_VDDIO ST 1
47 GND n/a Tied to common GND Ground - - 2
48 CSI_B_D0_P CSI_B_D0_P CSI Data Lane 2 (+) for Camera 1 Output +1.2V_GEN_AVDD CSI 3
49 GPIO_PU3 GPIO_PU3 GPIO PU3: Available for general use Bidir +1.8V_VDDIO ST 1
50 PWR_I2C_SCL PWR_I2C_SCL Power I2C Clock: For Nvidia use only Input, Open Drain +1.8V_VDDIO DD 2
51 CSI_B_D0_N CSI_B_D0_N CSI Data Lane 2 (-) for Camera 1 Output +1.2V_GEN_AVDD CSI 3
52 GPIO_PU4 GPIO_PU4 GPIO PU4: Available for general use Bidir +1.8V_VDDIO ST 1
53 PWR_I2C_SDA PWR_I2C_SDA Power I2C Data: For Nvidia use only Bidir, Open Drain +1.8V_VDDIO DD 2
54 GND n/a Tied to common GND Ground - - 3
55 GPIO_PU5 GPIO_PU5 GPIO PU5: Available for general use Bidir +1.8V_VDDIO ST 1
56 GEN1_I2C_SCL GEN1_I2C_SCL GEN1 I2C Clock: 1.8V I2C IF available for general use Input, Open Drain +1.8V_VDDIO DD 2
57 CAM1_GPIO GPIO_PCC1 GPIO for Camera 1 Bidir +1.8V_RUN_CAM ST 3
58 GPIO_PU6 GPIO_PU6 GPIO PU6: Available for general use Bidir +1.8V_VDDIO ST 1
59 GEN1_I2C_SDA GEN1_I2C_SDA GEN1 I2C Data: 1.8V I2C IF available for general use Bidir, Open Drain +1.8V_VDDIO DD 2
60 CAM1_AF_PWDN GPIO_PBB7 Autofocus Powerdown for Camera 1 Input +1.8V_RUN_CAM ST 3
61 ONKEY_L KB_COL0 (indirect) Power On (to PMU ONKEY & gated version to Tegra) Bidir +2.5V_AON_RTC - 1
62 GND n/a Tied to common GND Ground - - 2
63 CAM_FLASH GPIO_PB4 Flash enable to control camera flash driver Input +1.8V_RUN_CAM ST 3
64 PMU_RESET_IN_L n/a System Reset signal Bidir +2.5V_AON_RTC - 1
65 UART2_RXD UART2_RXD UART 2 Receive Output +1.8V_VDDIO ST 2
66 CAM1_PWDN GPIO_PBB5 Powerdown for Camera 1 Input +1.8V_RUN_CAM ST 3
67 FORCE_RECOVERY_L GPIO_PI1 (indirect) Force Recovery: To enter Forced Recovery mode Bidir +2.5V_AON_RTC - 1
68 UART2_TXD UART2_TXD UART 2 Transmit Input +1.8V_VDDIO ST 2
69 CAM1_MCLK CAM_MCLK Master Reference Clock for Camera 1 Input +1.8V_RUN_CAM ST 3
70 CLK3_OUT CLK3_OUT Clock 3 Output: Available clock source from Tegra K1 Input +1.8V_RUN_CAM ST 1
71 UART2_CTS_L UART2_CTS_L UART 2 Clear to Send Output +1.8V_VDDIO ST 2
72 NC n/a Not used - - - 3
73 GND n/a Tied to common GND Ground - - 1
74 UART2_RTS_L UART2_RTS_L UART 2 Request to Send Input +1.8V_VDDIO ST 2
75 NC n/a Not used - - - 3

技术分享

 关于GPIO和其他相关资源相关

1：http://elinux.org/Jetson/GPIO

2：http://elinux.org/Jetson/Tutorials/GPIO

3：http://elinux.org/Jetson/Tutorials/Vision-controlled_GPIO#Testing_GPIO_on_Jetson_TK1

 

TK1 ~ 控制GPIO


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